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PSoC
®
5: CY8C55 Family Datasheet
Programmable System-on-Chip (PSoC
®
)
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-66235 Rev. *D Revised February 15, 2012
General Description
With its unique array of configurable blocks, PSoC
®
5 is a true system-level solution providing microcontroller unit (MCU), memory,
analog, and digital peripheral functions in a single chip. The CY8C55 family offers a modern method of signal acquisition, signal
processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples
(near DC voltages) to ultrasonic signals. The CY8C55 family can handle dozens of data acquisition channels and analog inputs on
every GPIO pin. The CY8C55 family is also a high-performance configurable digital system with some part numbers including
interfaces such as USB, and multimaster I
2
C. In addition to communication interfaces, the CY8C55 family has an easy to configure
logic array, flexible routing to all I/O pins, and a high-performance 32-bit ARM
®
Cortex™-M3 microprocessor core. Designers can
easily create system-level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator™, a
hierarchical schematic design entry tool. The CY8C55 family provides unparalleled opportunities for analog and digital bill of materials
integration while easily accommodating last minute design changes through simple firmware updates.
Features
■ 32-bit ARM Cortex-M3 CPU core
❐ DC to 67 MHz operation
❐ Flash program memory, up to 256 KB, 100,000 write cycles,
20-year retention, and multiple security features
❐ Up to 64 KB SRAM memory
❐ 128 bytes of cache memory
❐ 2-KB electrically erasable programmable read-only memory
(EEPROM) memory, 1 million cycles, and 20 years retention
❐ 24-channel direct memory access (DMA) with multilayer
AMBA high-performance bus (AHB) bus access
• Programmable chained descriptors and priorities
• High bandwidth 32-bit transfer support
■ Low voltage, ultra low power
❐ Operating voltage range:2.7 V to 5.5 V
❐ 6 mA at 6 MHz
❐ Low power modes including:
• 2-µA sleep mode
• 300-nA hibernate mode with RAM retention
■ Versatile I/O system
❐ 46 to 70 I/Os (60 GPIOs, 8 SIOs, 2 USBIOs)
❐ Any GPIO to any digital or analog peripheral routability
❐ LCD direct drive from any GPIO, up to 46×16 segments
❐ CapSense
®
support from any GPIO
[1]
❐ 1.2 V to 5.5 V I/O interface voltages, up to 4 domains
❐ Maskable, independent IRQ on any pin or port
❐ Schmitt-trigger transistor-transistor logic (TTL) inputs
❐ All GPIOs configurable as open drain high/low,
pull-up/pull-down, High-Z, or strong output
❐ 25 mA sink on SIO
■ Digital peripherals
❐ 20 to 24 programmable logic device (PLD) based universal
digital blocks (UDBs)
❐ Full-Speed (FS) USB 2.0 12 Mbps using a 24 MHz external
oscillator
❐ Four 16-bit configurable timers, counters, and PWM blocks
❐ 67 MHz, 24-bit fixed point digital filter block (DFB) to
implement finite impulse response (FIR) and infinite impulse
response (IIR) filters
❐ Library of standard peripherals
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
• SPI, UART, and I
2
C
• Many others available in catalog
❐ Library of advanced peripherals
• Cyclic redundancy check (CRC)
• Pseudo random sequence (PRS) generator
• Local interconnect network (LIN) bus 2.0
• Quadrature decoder
■ Analog peripherals (2.7 V V
DDA
5.5 V)
❐ 1.024 V ±1% internal voltage reference
❐ Configurable delta-sigma ADC with 8- to 20-bit resolution
• Sample rates up to 192 ksps
• Programmable gain stage: ×0.25 to ×16
• 12-bit mode, 192 ksps, 66-dB signal to noise and distortion
ratio (SINAD), ±1-bit INL/DNL
• 16-bit mode, 48 ksps, 84-dB SINAD, ±2-bit INL, ±1-bit DNL
❐ Two SAR ADCs, each 12-bit at 700 ksps
❐ Four 8-bit 5.5 Msps current IDACs or 1-Msps voltage VDACs
❐ Four comparators with 95-ns response time
❐ Four uncommitted opamps with 10-mA drive capability
❐ Four configurable multifunction analog blocks. Example
configurations are programmable gain amplifier (PGA),
transimpedance amplifier (TIA), mixer, and Sample and Hold
❐ CapSense support
■ Programming, debug, and trace
❐ Single-wire debug (SWD) and single wire viewer (SWV)
interfaces
❐ Cortex-M3 flash patch and breakpoint (FPB) block
❐ Cortex-M3 data watchpoint and trace (DWT) generates data
trace information
❐ Cortex-M3 Instrumentation Trace Macrocell (ITM) can be
used for printf-style debugging
❐ DWT and ITM blocks communicate with off-chip debug and
trace systems via the SWV interface
❐ Bootloader programming supportable through I
2
C, SPI,
UART, USB, and other interfaces
■ Precision, programmable clocking
❐ 3 to 48 MHz internal oscillator over full temperature and
voltage range
❐ 4- to 25 MHz crystal oscillator for crystal PPM accuracy
❐ Internal PLL clock generation up to 67 MHz
❐ 32.768 kHz watch crystal oscillator
❐ Low power internal oscillator at 1, 33, and 100 kHz
■ Temperature and packaging
❐ –40 °C to +85 °C industrial temperature
❐ 68-pin QFN and 100-pin TQFP package options.
Notes
1. GPIOs with opamp outputs are not recommended for use with CapSense.
Verzeichnis
- ・ Konfiguration des Pinbelegungsdiagramms on Seite 9 Seite 80
- ・ Abmessungen des Paketumrisses on Seite 104 Seite 105
- ・ Teilenummerierungssystem on Seite 102
- ・ Blockdiagramm on Seite 3 Seite 8 Seite 10 Seite 20 Seite 26
- ・ Typisches Anwendungsschaltbild on Seite 110
- ・ Schweißen Temperatur on Seite 104
- ・ Beschreibung der Funktionen on Seite 1 Seite 18 Seite 36 Seite 44 Seite 46
- ・ Technische Daten on Seite 30 Seite 57 Seite 58 Seite 59 Seite 60
- ・ Anwendungsbereich on Seite 52
- ・ Elektrische Spezifikation on Seite 57
