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ASIC/FPGA
High Speed
I/O
Backplane/Cable
Sub-system
Switch Fabric Card
Line Card
OUT IN
DS32EV100
OUT IN
Tx
Tx
Rx
Rx
ASIC/FPGA
High Speed
I/O
DS32EV100
DS32EV100
www.ti.com
SNLS239D –OCTOBER 2006–REVISED FEBRUARY 2013
DS32EV100 Programmable Single Equalizer
Check for Samples: DS32EV100
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FEATURES
DESCRIPTION
The DS32EV100 programmable equalizer provides
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• Equalizes Up to 14 dB loss at 3.2 Gbps
compensation for transmission medium losses and
• 8 levels of Programmable Equalization
reduces the medium-induced deterministic jitter for
• Operates up to 3.2 Gbps with 40” FR4 Traces
NRZ data channel. The DS32EV100 is optimized for
operation up to 3.2 Gbps for both cables and FR4
• 0.12 UI Residual Deterministic Jitter at 3.2
traces. The equalizer channel has eight levels of
Gbps with 40” FR4 Traces
input equalization that can be programmed by three
• Single 2.5V or 3.3V Power Supply
control pins.
• Supports AC or DC-Coupling with Wide Input
The equalizer supports both AC and DC-coupled data
Common-Mode
paths for long run length data patterns such as
• Low power Consumption: 100 mW Typ at 2.5V
PRBS-31, and balanced codes such as 8b/10b. The
device uses differential current-mode logic (CML)
• Small 3 mm x 4 mm 14-pin WSON Package
inputs and outputs. The DS32EV100 is available in a
• > 8 kV HBM ESD Rating
3 mm x 4 mm 14-pin WSON package. Power is
• -40 to 85°C Operating Temperature Range
supplied from either a 2.5V or 3.3V supply.
Simplified Application Diagram
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Verzeichnis
- ・ Konfiguration des Pinbelegungsdiagramms on Seite 2
- ・ Abmessungen des Paketumrisses on Seite 10 Seite 12 Seite 13
- ・ Markierungsinformationen on Seite 10
- ・ Blockdiagramm on Seite 6
- ・ Beschreibung der Funktionen on Seite 6
- ・ Technische Daten on Seite 3
- ・ Anwendungsbereich on Seite 6 Seite 15
- ・ Elektrische Spezifikation on Seite 3 Seite 4 Seite 5
